Parallel processing is effective to improve the processing speed of the information processing system. In parallel processing system, a plurality of processing units (CPU: Central Processing Unit) share the process. In addition, in order to improve the processing speed of the CPU, a cache memory) is provided between the CPU and a main memory. The cache memory holds data, its address and status of which the CPU would access among the data stored in the main memory, and is configured of a high-speed and a small-capacity memory. The cache memory executes an input and output of the data behalf of the main memory of which the CPU originally accesses.
Because the cache memory automatically stores the data and performs an alternative operation of the main memory, program of the CPU is no need to be aware of the cache memory. In recent years, according to an improvement of integration of LSI (Large Scale Integrated) and an increase in the demand speed of the device, the cache memory is provided in the CPU chip.
In SMP (Symmetric Multi-Processing) system among the parallel processing system, one CPU performs a snoop to search contents which are registered in the cache memory of the other CPU. To prevent interference of the cache memory which is caused the snoop between the CPUs, synchronization mechanism of the cache memory of the CPU is provided.
When processing consecutive requests to the same cache address, the synchronization mechanism of the cache memory retries a subsequent request which arrives before an update of the cache management information on an preceding request is not completed. This control is referred to as busy control. The SMP system has set a uniform monitoring range of the busy to all CPU chips.